An Analytical Metal Resistance Model and Its Application for Sub-22-nm Metal-Gate CMOS
- X. Miao
- Ruqiang Bao
- et al.
- 2015
- IEEE Electron Device Letters
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A review of III-V planar nanowire arrays: Selective lateral VLS epitaxy and 3D transistors
- Chen Zhang
- Xin Miao
- et al.
- 2017
- Journal of Physics D: Applied Physics
III-V nanowire transistors for low-power logic applications: A review and outlook
- Chen Zhang
- Xiuling Li
- 2016
- IEEE T-ED