Cell selection for high-performance designs in an industrial design flow
- Tiago J. Reimann
- Cliff Sze
- et al.
- 2016
- ISPD 2016
Publications
Date
Featured collections
Popular topics
5 results for Ricardo Reis
Gate sizing and threshold voltage assignment for high performance microprocessor designs
- Tiago J. Reimann
- Cliff Sze
- et al.
- 2015
- ASP-DAC 2015
Maze routing steiner trees with effective critical sink optimization
- Renato F. Hentschke
- Jaganathan Narasimham
- et al.
- 2007
- ISPD 2007
Challenges of cell selection algorithms in industrial high performance microprocessor designs
- Tiago J. Reimann
- Cliff Sze
- et al.
- 2016
- Integration, the VLSI Journal
Maze routing steiner trees with delay versus wire length tradeoff
- Renato Hentschke
- Jaganathan Narasimhan
- et al.
- 2009
- IEEE Transactions on VLSI Systems