Scalable, efficient ASICS for the square kilometre array: From A/D conversion to central correlation
- Martin L. Schmatz
- Rik Jongerius
- et al.
- 2014
- ICASSP 2014
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61 results for Peter Buchmann
A deep trench capacitor based 2:1 and 3:2 reconfigurable on-chip switched capacitor DC-DC converter in 32 nm SOI CMOS
- Toke M. Andersen
- Florian Krismer
- et al.
- 2014
- APEC 2014
A 16Gb/s 3.7mW/Gb/s 8-tap DFE receiver and baud rate CDR with 30kppm tracking bandwidth
- Pier Andrea Francese
- Thomas Toifl
- et al.
- 2013
- A-SSCC 2013
A 4.6W/mm2 power density 86% efficiency on-chip switched capacitor DC-DC converter in 32 nm SOI CMOS
- Toke M. Andersen
- Florian Krismer
- et al.
- 2013
- APEC 2013
A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS
- Thomas Toifl
- Michael Ruegg
- et al.
- 2012
- VLSI Circuits 2012
A 2.6mW/Gbps 12.5Gbps RX with 8-tap switched-cap DFE in 32nm CMOS
- Thomas Toifl
- Christian Menolfi
- et al.
- 2011
- VLSI Circuits 2011
A small-area voltage regulator with high-bandwidth supply-rejection using a regulated replica in 45nm CMOS SOI
- Thomas Toifl
- Christian Menolfi
- et al.
- 2008
- A-SSCC 2008
A low-power 40 Gbit/s receiver circuit based on full-swing CMOS-style clocking
- Thomas Toifl
- Christian Menolfi
- et al.
- 2007
- CSICS 2007
Electrical and optical transceivers for short-range data communication, fabricated in VLSI 90-nm bulk and SOI CMOS technology
- Thomas Morf
- Christian Menolfi
- et al.
- 2005
- CSICS 2005
A 22 Gbit/s PAM-4 receiver in 90nm CMOS-SOI technology
- Thomas Toifl
- Christian Menolfi
- et al.
- 2005
- VLSI Circuits 2005