Selective Enablement of Dual Dipoles for near Bandedge Multi-Vt Solution in High Performance FinFET and Nanosheet Technologies
- Ruqiang Bao
- K. Watanabe
- et al.
- 2020
- VLSI Technology 2020
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26 results for Huimei Zhou
Analysis of BTI, SHE Induced BTI and HCD under Full VG/VD Space in GAA Nano-Sheet N and P FETs
- Nilotpal Choudhury
- Uma Sharma
- et al.
- 2020
- IRPS 2020
A new technique for evaluating stacked nanosheet inner spacer TDDB reliability
- Tian Shen
- K. Watanabe
- et al.
- 2020
- IRPS 2020
NBTI Impact of Surface Orientation in Stacked Gate-All-Around Nanosheet Transistor
- Huimei Zhou
- Miaomiao Wang
- et al.
- 2020
- IRPS 2020
Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications
- J. Zhang
- S. Pancharatnam
- et al.
- 2019
- IEDM 2019
Multiple-Vt Solutions in Nanosheet Technology for High Performance and Low Power Applications
- Ruqiang Bao
- Reinaldo A. Vega
- et al.
- 2019
- IEDM 2019
A Novel Dry Selective Etch of SiGe for the Enablement of High Performance Logic Stacked Gate-All-Around NanoSheet Devices
- Nicolas Loubet
- T. Devarajan
- et al.
- 2019
- IEDM 2019
Self-Allancd Gate Contact (SAGC) for CMOS technology scaling beyond 7nm
- Ruilong Xie
- Chanro Park
- et al.
- 2019
- VLSI Technology 2019
Direct Partition Measurement of Parasitic Resistance Components in Advanced Transistor Architectures
- Zuoguang Liu
- Heng Wu
- et al.
- 2019
- VLSI Technology 2019
Gate-Cut-Last in RMG to Enable Gate Extension Scaling and Parasitic Capacitance Reduction
- A. Greene
- Huimei Zhou
- et al.
- 2019
- VLSI Technology 2019