Self-Allancd Gate Contact (SAGC) for CMOS technology scaling beyond 7nm
- Ruilong Xie
- Chanro Park
- et al.
- 2019
- VLSI Technology 2019
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31 results for Veeraraghavan Basker
Bias Temperature Instability Reliability in Stacked Gate-All-Around Nanosheet Transistor
- Miaomiao Wang
- Jingyun Zhang
- et al.
- 2019
- IRPS 2019
Channel Geometry Impact and Narrow Sheet Effect of Stacked Nanosheet
- Chun Wing Yeung
- Jingyun Zhang
- et al.
- 2018
- IEDM 2018
Si nanowire CMOS fabricated with minimal deviation from RMG FinFET technology showing record performance
- Isaac Lauer
- Nicolas Loubet
- et al.
- 2015
- VLSI Technology 2015
A novel ALD SiBCN low-k spacer for parasitic capacitance reduction in FinFETs
- Tenko Yamashita
- S. Mehta
- et al.
- 2015
- VLSI Technology 2015
High performance 14nm SOI FinFET CMOS technology with 0.0174μm2 embedded DRAM and 15 levels of Cu metallization
- C.-H.C-H. Lin
- Brian Greene
- et al.
- 2014
- IEDM 2014
Comprehensive study of effective current variability and MOSFET parameter correlations in 14nm multi-fin SOI FINFETs
- Abhijeet Paul
- Andres Bryant
- et al.
- 2013
- IEDM 2013
Fin width scaling for improved short channel control and performance in aggressively scaled channel length SOI finFETs
- Abhijeet Paul
- Chun-Chen Yeh
- et al.
- 2013
- S3S 2013
Aggressively scaled strained silicon directly on insulator (SSDOI) FinFETs
- A. Khakifirooz
- R. Sreenivasan
- et al.
- 2013
- S3S 2013
Channel doping impact on FinFETs for 22nm and beyond
- Chung-Hsun Lin
- R. Kambhampati
- et al.
- 2012
- VLSI Technology 2012