2nd Generation dual-channel optimization with cSiGe for 22nm HP technology and beyond
- C. Ortolland
- Daniel Jaeger
- et al.
- 2013
- IEDM 2013
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5 results for Claude Ortolland
22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL
- S. Narasimha
- P. Chang
- et al.
- 2012
- IEDM 2012
Titanium silicide/titanium nitride full metal gates for dual-channel gate-first CMOS
- Martin M. Frank
- Cyril Cabral
- et al.
- 2016
- IEEE Electron Device Letters
A novel low resistance gate fill for extreme gate length scaling at 20nm and beyond for gate-last high-k/metal gate CMOS technology
- U. Kwon
- K. Wong
- et al.
- 2012
- VLSI Technology 2012
Overview of anneal technology for advanced logic CMOS
- Claude Ortolland
- 2011
- IWJT 2011