An on-chip dual supply charge pump system for 45nm PD SOI eDRAM
- J.B. Kuang
- A. Mathews
- et al.
- 2008
- ESSCIRC 2008
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20 results for D.W. Plass
A low power and high performance SOI SRAM circuit design with improved cell stability
- R.V. Joshi
- Y. Chan
- et al.
- 2006
- IEEE SOI 2006
Statistical exploration of the dual supply voltage space of a 65nm PD/SOI CMOS SRAM cell
- Rajiv Joshi
- Rouwaida Kanj
- et al.
- 2006
- ESSDERC 2006
Variability analysis for sub-100 nm PD/SOI CMOS SRAM cell
- Rajiv V. Joshi
- Saibal Mukhopadhyay
- et al.
- 2004
- ESSCIRC 2004
Design and implementation of the POWER5™ microprocessor
- Joachim Clabes
- Joshua Friedrich
- et al.
- 2004
- ICICDT 2004
IBM z13 circuit design and methodology
- J. Warnock
- Christopher Berry
- et al.
- 2015
- IBM J. Res. Dev
IBM POWER8 circuit design and energy optimization
- Victor Zyuban
- Joshua Friedrich
- et al.
- 2015
- IBM J. Res. Dev
Circuit and physical design of the zenterprise™ ec12 microprocessor chips and multi-chip module
- James Warnock
- Yuen Chan
- et al.
- 2014
- IEEE Journal of Solid-State Circuits
A 45 nm SOI embedded DRAM macro for the POWER™ processor 32 MByte on-chip L3 cache
- John Barth
- Don Plass
- et al.
- 2011
- IEEE Journal of Solid-State Circuits
Design of sub-90 nm low-power and variation tolerant PD/SOI SRAM cell based on dynamic stability metrics
- Rajiv V. Joshi
- Saibal Mukhopadhyay
- et al.
- 2009
- IEEE Journal of Solid-State Circuits