Resistivity of copper interconnects beyond the 7 nm node
- Adam Pyzyna
- Robert L. Bruce
- et al.
- 2015
- VLSI Technology 2015
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144 results for Lynne Gignac
III-V device integration on Si using template-assisted selective epitaxy
- Heinz Schmid
- Mattias Borg
- et al.
- 2015
- DRC 2015
Template-assisted selective epitaxy of III-V nanoscale devices for co-planar heterogeneous integration with Si
- Heinz Schmid
- Mattias Borg
- et al.
- 2015
- Applied Physics Letters
Vertical InAs-Si gate-all-around tunnel FETs integrated on Si using selective epitaxy in nanotube templates
- D. Cutaia
- Kirsten E. Moselund
- et al.
- 2015
- IEEE J-EDS
Fabrication and analysis of vertical p-type InAs-Si nanowire tunnel FETs
- D. Cutaia
- Kirsten E. Moselund
- et al.
- 2015
- EUROSOI-ULIS 2015
Electrical characterization of FinFETs with fins formed by directed self assembly at 29 nm fin pitch using a self-aligned fin customization scheme
- Hsinyu Tsai
- Hiroyuki Miyazoe
- et al.
- 2014
- IEDM 2014
High energy BSE/SE/STEM imaging of 8 um thick semiconductor interconnects
- L. Gignac
- C. Beslin
- et al.
- 2014
- Microscopy and Microanalysis
Fabrication of sub-20 nm nanopore arrays in membranes with embedded metal electrodes at wafer scales
- Jingwei Bai
- Deqiang Wang
- et al.
- 2014
- Nanoscale
Full thermoelectric characterization of InAs nanowires using MEMS heater/sensors
- Siegfried F. Karg
- V. Troncale
- et al.
- 2014
- Nanotechnology
Vertical III-V nanowire device integration on Si(100)
- Mattias Borg
- Heinz Schmid
- et al.
- 2014
- Nano Letters