3D integration ESD protection design and analysis
- Souvick Mitra
- Ephrem Gebreselasie
- et al.
- 2015
- EOS/ESD 2015
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30 results for Joel Silberman
Characterization of TSV-induced loss and substrate noise coupling in advanced three-dimensional CMOS SOI technology
- Xiaoxiong Gu
- Joel A. Silberman
- et al.
- 2013
- IEEE Transactions on CPMT
Mitigating TSV-induced substrate noise coupling in 3-D IC using buried interface contacts
- Xiaoxiong Gu
- Joel Silberman
- et al.
- 2012
- EPEPS 2012
A shorted global clock design for multi-GHz 3D stacked chips
- Liang-Teck Pang
- Phillip J. Restle
- et al.
- 2012
- VLSI Circuits 2012
A 3D system prototype of an eDRAM cache stacked over processor-like logic using through-silicon vias
- Matt Wordeman
- Joel Silberman
- et al.
- 2012
- ISSCC 2012
Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI
- Brian Flachs
- Shigehiro Asano
- et al.
- 2007
- IBM J. Res. Dev
The circuits and physical design of the synergistic processor element of a CELL processor
- O. Takahashi
- R. Cook
- et al.
- 2005
- VLSI Circuits 2005
Reducing power consumption during TLB lookups in a PowerPC/spl trade/ embedded processor
- Shivakumar Swaminathan
- Sanjay B. Patel
- et al.
- 2005
- ISQED 2005
The circuit design of the synergistic processor element of a CELL processor
- O. Takahashi
- R. Cook
- et al.
- 2005
- ICCAD 2005
Power-conscious design of the cell processor's synergistic processor element
- Osamu Takahashi
- Scott Cottier
- et al.
- 2005
- IEEE Micro