ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08μm2 SRAM cell
- Kangguo Cheng
- A. Khakifirooz
- et al.
- 2011
- VLSI Technology 2011
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74 results for Juntao Li
ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08μm2 SRAM cell
- Kangguo Cheng
- A. Khakifirooz
- et al.
- 2011
- VLSI Circuits 2011
Full metal gate with borderless contact for 14 nm and beyond
- Soon-Cheon Seo
- L.F. Edge
- et al.
- 2011
- VLSI Technology 2011
Impact of back bias on ultra-thin body and BOX (UTBB) devices
- Q. Liu
- Frederic Monsieur
- et al.
- 2011
- VLSI Technology 2011
Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drain
- K. Cheng
- A. Khakifirooz
- et al.
- 2009
- VLSI Technology 2009
Effect of ion implantation and anneals on fully-strained SiC and SiC:P films using multiple characterization techniques
- A. Madan
- J. Li
- et al.
- 2008
- ECS Meeting 2008
Recent progress and challenges in enabling embedded Si:C technology
- B. Yang
- Z. Ren
- et al.
- 2008
- ECS Meeting 2008
In-line Raman spectroscopy for gate-all-around nanosheet device manufacturing
- Daniel Schmidt
- Curtis Durfee
- et al.
- 2022
- JM3
Improved Air Spacer for Highly Scaled CMOS Technology
- Kangguo Cheng
- Chanro Park
- et al.
- 2020
- IEEE Transactions on Electron Devices
Strain, stress, and mechanical relaxation in fin-patterned Si/SiGe multilayers for sub-7 nm nanosheet gate-all-around device technology
- S. Reboh
- R. Coquand
- et al.
- 2018
- Applied Physics Letters