An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS
- Mark Ferriss
- Jean-Olivier Plouchart
- et al.
- 2012
- VLSI Circuits 2012
Publications
Date
Featured collections
Popular topics
69 results for Daniel Friedman
A 21.8-27.5GHz PLL in 32nm SOI using G m linearization to achieve -130dBc/Hz phase noise at 10MHz offset from a 22GHz carrier
- Bodhisatwa Sadhu
- Mark A. Ferriss
- et al.
- 2012
- RFIC 2012
A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology
- John Bulzacchelli
- Troy Beukema
- et al.
- 2012
- ISSCC 2012
A compact low-power 3D I/O in 45nm CMOS
- Yong Liu
- Wing Luk
- et al.
- 2012
- ISSCC 2012
A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS
- Ankur Agrawal
- John Bulzacchelli
- et al.
- 2012
- ISSCC 2012
Dual-loop system of distributed microregulators with high DC accuracy, load response time below 500 ps, and 85-mV dropout voltage
- John F. Bulzacchelli
- Zeynep Toprak-Deniz
- et al.
- 2012
- IEEE Journal of Solid-State Circuits
An 8x 10-Gb/s source-synchronous I/O system based on high-density silicon carrier interconnects
- Timothy O. Dickson
- Yong Liu
- et al.
- 2012
- IEEE Journal of Solid-State Circuits
High-density silicon carrier transmission line design for chip-to-chip interconnects
- Xiaoxiong Gu
- Lavanya Turlapati
- et al.
- 2011
- EPEPS 2011
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons
- Jae-Sun Seo
- Bernard Brezzo
- et al.
- 2011
- CICC 2011
An 8x10-Gb/s source-synchronous I/O system based on high-density silicon carrier interconnects
- Timothy O. Dickson
- Yong Liu
- et al.
- 2011
- VLSI Circuits 2011