Dual-loop system of distributed microregulators with high DC accuracy, load response time below 500ps, and 85mV dropout voltage
- Zeynep Toprak-Deniz
- John Bulzacchelli
- et al.
- 2011
- VLSI Circuits 2011
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69 results for Daniel Friedman
A compact 6 GHz to 12 GHz digital PLL with coupled dual-LC tank DCO
- A. Goel
- Alexander V. Rylyakov
- et al.
- 2010
- VLSI Circuits 2010
A DPLL-based per core variable frequency clock generator for an eight-core POWER7™ microprocessor
- Jose Tierno
- Alexander Rylyakov
- et al.
- 2010
- VLSI Circuits 2010
A 10-Gb/s compact low-power serial I/O with DFE-IIR equalization in 65-nm CMOS
- Byungsub Kim
- Yong Liu
- et al.
- 2009
- IEEE Journal of Solid-State Circuits
A 19gb/s 38mW 1-tap speculative DFE receiver in 90nm CMOS
- Didem Z. Turker
- Alexander Rylyakov
- et al.
- 2009
- VLSI Circuits 2009
A 7.5-GS/s 3.8-ENOB 52-mW flash ADC with clock duty cycle control in 65nm CMOS
- Hayun Chung
- Alexander Rylyakov
- et al.
- 2009
- VLSI Circuits 2009
Bang-bang digital PLLS at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications
- A. Rylyakov
- J. Tierno
- et al.
- 2009
- ISSCC 2009
A 5.4mW 0.0035mm2 0.48psrms-jitter 0.8-to-5GHz non-PLL/DLL all-digital phase generator/rotator in 45nm SOI CMOS
- Kyu-Hyoun Kim
- Daniel M. Dreps
- et al.
- 2009
- ISSCC 2009
A 12-Gb/s 11-mW half-rate sampled 5-tap decision feedback equalizer with current-integrating summers in 45-nm SOI CMOS technology
- Timothy O. Dickson
- John F. Bulzacchelli
- et al.
- 2009
- IEEE Journal of Solid-State Circuits
A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS
- John F. Bulzacchelli
- Timothy O. Dickson
- et al.
- 2009
- ISSCC 2009