A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS
- Yong Liu
- Byungsub Kim
- et al.
- 2009
- ISSCC 2009
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69 results for Daniel Friedman
A wide tuning range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45nm SOI
- Alexander Rylyakov
- Jose Tierno
- et al.
- 2008
- CICC 2008
A 12-Gb/s 11-mW half-rate sampled 5-tap decision feedback equalizer with current-integrating summers in 45-nm SOI CMOS technology
- Timothy O. Dickson
- John F. Bulzacchelli
- et al.
- 2008
- VLSI Circuits 2008
A 2.6mW 370MHz-to-2.5GHz open-loop quadrature clock generator
- Kyu-Hyoun Kim
- Paul W. Coteus
- et al.
- 2008
- ISSCC 2008
A modular all-digital PLL architecture enabling both 1-to-2GHz and 24-to-32GHz operation in 65NM CMOS
- A. Rylyakov
- J. Tierno
- et al.
- 2008
- ISSCC 2008
A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI
- José A. Tierno
- Alexander V. Rylyakov
- et al.
- 2008
- IEEE Journal of Solid-State Circuits
A uniform bandwidth PLL using a continuously tunable single-input dual-path LC VCO for 5Gb/s PCI express Gen2 application
- Woogeun Rhee
- Herschel Ainspan
- et al.
- 2007
- A-SSCC 2007
Impact of SOI history effect on random data signals
- Keith A. Jenkins
- S. Kim
- et al.
- 2007
- ICICDT 2007
Power-efficient decision-feedback equalizers for multi-Gb/s CMOS serial links (invited)
- John F. Bulzacchelli
- Alexander V. Rylyakov
- et al.
- 2007
- RFIC 2007
An ultra-compact differentially tuned 6-GHz CMOS LC-VCO with dynamic common-mode feedback
- Babak Soltanian
- Herschel Ainspan
- et al.
- 2007
- IEEE Journal of Solid-State Circuits