A wide tuning range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45nm SOI
- Alexander Rylyakov
- Jose Tierno
- et al.
- 2008
- CICC 2008
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69 results for Daniel Friedman
A 12-Gb/s 11-mW half-rate sampled 5-tap decision feedback equalizer with current-integrating summers in 45-nm SOI CMOS technology
- Timothy O. Dickson
- John F. Bulzacchelli
- et al.
- 2008
- VLSI Circuits 2008
A uniform bandwidth PLL using a continuously tunable single-input dual-path LC VCO for 5Gb/s PCI express Gen2 application
- Woogeun Rhee
- Herschel Ainspan
- et al.
- 2007
- A-SSCC 2007
Impact of SOI history effect on random data signals
- Keith A. Jenkins
- S. Kim
- et al.
- 2007
- ICICDT 2007
Power-efficient decision-feedback equalizers for multi-Gb/s CMOS serial links (invited)
- John F. Bulzacchelli
- Alexander V. Rylyakov
- et al.
- 2007
- RFIC 2007
An ultra compact differentially tuned 6 GHz CMOS LC VCO with dynamic common-mode feedback
- Babak Soltanian
- Herschel Ainspan
- et al.
- 2006
- CICC 2006
A low-power receiver with switched-capacitor summation DFE
- Azita Emami-Neyestanak
- Aida Varzaghani
- et al.
- 2006
- VLSI Circuits 2006
A 0.18-μm SiGe BiCMOS Receiver and Transmitter Chipset for SONET OC-768 Transmission Systems
- Mounir Meghelli
- Alexander V. Rylyakov
- et al.
- 2003
- IEEE Journal of Solid-State Circuits
A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop
- Woogeun Rhee
- Herschel Ainspan
- et al.
- 2003
- CICC 2003
45-Gb/s SiGe BiCMOS PRBS generator and PRBS checker
- Seongwon Kim
- Mohit Kapur
- et al.
- 2003
- CICC 2003