Phase and amplitude pre-emphasis techniques for low-power serial links
- James F. Buckwalter
- Mounir Meghelli
- et al.
- 2006
- IEEE Journal of Solid-State Circuits
Publications
71 results for Daniel Friedman
A Semi-Digital Delay-Locked Loop Using an Analog-Based Finite State Machine
- Woogeun Rhee
- Benjamin Parker
- et al.
- 2004
- IEEE TCAS-II
A 0.18-μm SiGe BiCMOS Receiver and Transmitter Chipset for SONET OC-768 Transmission Systems
- Mounir Meghelli
- Alexander V. Rylyakov
- et al.
- 2003
- IEEE Journal of Solid-State Circuits
45-Gb/s SiGe BiCMOS PRBS generator and PRBS checker
- Seongwon Kim
- Mohit Kapur
- et al.
- 2003
- CICC 2003
A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop
- Woogeun Rhee
- Herschel Ainspan
- et al.
- 2003
- CICC 2003
A 0.18μm SiGe BiCMOS receiver and transmitter chipset for SONET OC-768 transmission systems
- Mounir Meghelli
- Alexander V. Rylyakov
- et al.
- 2003
- ISSCC 2003
SiGe BiCMOS integrated circuits for high-speed serial communication links
- Daniel J. Friedman
- Mounir Meghelli
- et al.
- 2003
- IBM J. Res. Dev
A single-chip 12.5Gbaud transceiver for serial data communication
- D. Friedman
- M. Meghelli
- et al.
- 2001
- VLSI Circuits 2001
Noise performance and considerations for integrated RF/analog/mixed-signal design in a high-performance SiGe BiCMOS technology
- D.R. Greenberg
- S. Sweeney
- et al.
- 2001
- Technical Digest - International Electron Devices Meeting
Sub-picosecond jitter SiGe BiCMOS transmit and receive PLLs for 12.5 Gbaud serial data communication
- D. Friedman
- M. Meghelli
- et al.
- 2000
- VLSI Circuits 2000