Direct silicon bonded (DSB) substrate solid phase epitaxy (SPE) integration scheme study for high performance bulk CMOS
- Haizhou Yin
- C.Y. Sung
- et al.
- 2006
- IEDM 2006
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48 results for Mukesh Khare
Challenges and opportunities for high performance 32 nm CMOS technology
- J. Sleight
- I. Lauer
- et al.
- 2006
- IEDM 2006
High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL
- W.-H. Lee
- A. Waite
- et al.
- 2005
- IEDM 2005
A high performance 90 nm SOI technology with 0.992 μm2 6T-SRAM cell
- Mukesh Khare
- S. Ku
- et al.
- 2002
- IEDM 2002
High performance 0.18 μm SOI CMOS technology
- E. Leobandung
- E. Barth
- et al.
- 1999
- IEDM 1999
Gate-dielectric permitivity and metal-gate work-function tradeoff in Lmet = 25 nm PDSOI device characteristics
- Dechao Guo
- Andres Bryant
- et al.
- 2006
- IEEE Electron Device Letters
Effect of tensile uniaxial stress on the electron transport properties of deeply scaled FD-SOI n-type MOSFETs
- H. Nayfeh
- D. Singh
- et al.
- 2006
- IEEE Electron Device Letters
Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
- N. Loubet
- T.B. Hook
- et al.
- 2017
- VLSI Technology 2017
Bottom oxidation through STI (BOTS) - A novel approach to fabricate dielectric isolated FinFETs on bulk substrates
- K. Cheng
- S.-C. Seo
- et al.
- 2014
- VLSI Technology 2014
Dielectric isolated FinFETs on bulk substrate
- Darsen Lu
- Kangguo Cheng
- et al.
- 2014
- S3S 2014