Measurements of inter-and-intra device transient thermal transport on SOI FETs
- P. Solomon
- M. Shamsa
- et al.
- 2007
- IEDM 2007
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75 results for Christopher P. D’Emic
Enabling SOI-based assembly technology for three-dimensional (3D) integrated circuits (ICs)
- A. Topol
- D.C. La Tulipe
- et al.
- 2005
- IEDM 2005
Interface engineering for enhanced electron mobilities in W/HfO 2 gate stacks
- A.C. Callegari
- P. Jamison
- et al.
- 2004
- IEDM 2004
Charge trapping in aggressively scaled metal gate/high-κ stacks
- E. Gusev
- V. Narayanan
- et al.
- 2004
- IEDM 2004
Device Design Considerations for Ultra-Thin SOI MOSFETs
- B. Doris
- M. Ieong
- et al.
- 2003
- IEDM 2003
Tunnel Current Measurements on P/N Junction Diodes and Implications for Future Device Design
- Paul M. Solomon
- David J. Frank
- et al.
- 2003
- IEDM 2003
High Performance CMOS Fabricated on Hybrid Substrate with Different Crystal Orientations
- M. Yang
- M. Ieong
- et al.
- 2003
- IEDM 2003
80 nm poly-silicon gated n-FETs with ultra-thin Al2O3 gate dielectric for ULSI applications
- D.A. Buchanan
- E. Gusev
- et al.
- 2000
- IEDM 2000
Very high performance 50 nm CMOS at low temperature
- S.J. Wind
- L.T. Shi
- et al.
- 1999
- IEDM 1999
Effects of wafer cleaning reduction on metals removal and ultrathin gate oxide quality
- C. D'Emic
- S. Cohen
- et al.
- 1997
- MRS Spring Meeting 1997