Vref optimization in DDR4 RDIMMs for improved timing margins
- Saravanan Sethuraman
- Anil Lingambudi
- et al.
- 2014
- EDAPS 2014
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16 results for Kyu-Hyoun Kim
Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems
- Janani Mukundan
- Hillery Hunter
- et al.
- 2013
- ISCA 2013
A 5.4mW 0.0035mm2 0.48psrms-jitter 0.8-to-5GHz non-PLL/DLL all-digital phase generator/rotator in 45nm SOI CMOS
- Kyu-Hyoun Kim
- Daniel M. Dreps
- et al.
- 2009
- ISSCC 2009
A 2.6mW 370MHz-to-2.5GHz open-loop quadrature clock generator
- Kyu-Hyoun Kim
- Paul W. Coteus
- et al.
- 2008
- ISSCC 2008
An 8 Gb/s/pin 9.6 ns row-cycle 288 Mb deca-data rate SDRAM with an I/O error detection scheme
- Kyu-Hyoun Kim
- Hoe-Ju Chung
- et al.
- 2007
- IEEE Journal of Solid-State Circuits
A second order mixed-mode charge pump scheme for low phase/duty error and low power consumption
- Kyu-Hyoun Kim
- In-Young Chung
- 2007
- IEICE Transactions on Electronics