Power supply noise induced jitter estimation in high speed clock tree for full chip timing analysis
- Wen Yin
- Zegui Pang
- et al.
- 2013
- DesignCon 2013
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3 results for Wen Yin
Modeling and analysis of signal transmission with Through Silicon Via (TSV) noise coupling
- Zhenyang Chen
- Qin Wang
- et al.
- 2013
- ISCAS 2013
Auto-assign method for large scale flip-chip package design
- Haitao Han
- Wen Yin
- et al.
- 2011
- ASICON 2011