Influence of package parasitic elements on CDM stress
- James Di Sarro
- Bill Reynold
- et al.
- 2013
- EOS/ESD 2013
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9 results for James Di Sarro
Maximizing ESD robustness of current-mode-logic (CML) driver with internal gate bias network
- You Li
- James Di Sarro
- et al.
- 2013
- EOS/ESD 2013
Investigation of SOI SCR triggering and current sustaining under DC and TLP conditions
- Junjun Li
- James Di Sarro
- et al.
- 2013
- EOS/ESD 2013
Design and optimization of scr devices for on-chip esd protection in advanced SOI CMOS technologies
- Junjun Li
- James Di Sarro
- et al.
- 2012
- EOS/ESD 2012
Effect of embedded-sige eSiGeon ESD TLP and VFTLP characteristics of diode-triggered silicon controlled rectifiers DTSCRs
- Rahul Mishra
- Junjun Li
- et al.
- 2012
- EOS/ESD 2012
Pulsed gate dielectric breakdown in a 32 nm technology under different ESD stress configurations
- Yang Yang
- Robert Gauthier
- et al.
- 2010
- EOS/ESD 2010
Characterization of high-k/metal gate stack breakdown in the time scale of ESD events
- Yang Yang
- James Di Sarro
- et al.
- 2010
- IRPS 2010
ESD time-domain characterization of high-k gate dielectric in a 32 nm CMOS technology
- James Di Sarro
- Yang Yang
- et al.
- 2009
- EOS/ESD 2009
Evaluation of SCR-based ESD protection devices in 90nm and 65nm CMOS technologies
- James Di Sarro
- Kiran Chatty
- et al.
- 2007
- IRPS 2007