Comprehensive study of effective current variability and MOSFET parameter correlations in 14nm multi-fin SOI FINFETs
- Abhijeet Paul
- Andres Bryant
- et al.
- 2013
- IEDM 2013
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6 results for John Iacoponi
Novel approach to reduce source/drain series and contact resistance in high-performance UTSOI CMOS devices using selective electrodeless CoWP or CoB process
- James Pan
- Anna Topol
- et al.
- 2007
- IEEE Electron Device Letters
10nm FINFET technology for low power and high performance applications
- D. Guo
- H. Shang
- et al.
- 2014
- ICSICT 2014
The past, present and future of high-k/metal gates
- Kisik Choi
- Takashi Ando
- et al.
- 2013
- ECS Meeting 2013
Extremely scaled gate-first high-k/metal gate stack with EOT of 0.55 nm using novel interfacial layer scavenging techniques for 22nm technology node and beyond
- K. Choi
- H. Jagannathan
- et al.
- 2009
- VLSI Technology 2009
Novel approach to reduce source/drain series resistance in high performance CMOS devices using self-aligned CoWP process for 45nm node UTSOI transistors with 20nm gate length
- James Pan
- Anna Topol
- et al.
- 2006
- VLSI Technology 2006