Maximizing ESD robustness of current-mode-logic (CML) driver with internal gate bias network
- You Li
- James Di Sarro
- et al.
- 2013
- EOS/ESD 2013
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Predictive full circuit ESD simulation and analysis using extended ESD compact models: Methodology and tool implementation
- Junjun Li
- Robert Gauthier
- et al.
- 2010
- EOS/ESD 2010