Suppression of the SOI floating-body effects by linked-body device structure
- W. Chen
- Y. Taur
- et al.
- 1996
- VLSI Technology 1996
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83 results for Yuan Taur
CMOS technology evolution: from 1 μm to 0.1 μm
- Y. Taur
- 1995
- ICSICT 1995
Ultra-low power 0.1 μm CMOS
- Y. Mii
- S.J. Wind
- et al.
- 1994
- VLSI Technology 1994
High performance 0.1μm nMOSFET's with 10 ps/stage delay (85 K) at 1.5 V power supply
- Y. Mii
- S. Rishton
- et al.
- 1993
- VLSI Technology 1993
0.1 μm CMOS and beyond
- Yuan Taur
- Yuh-Jier Mii
- 1993
- VLSI-TSA 1993
A high performance BiCMOS technology using 0.25 μm CMOS and double poly 47 GHz bipolar
- G. Shahidi
- J. Warnock
- et al.
- 1992
- VLSI Technology 1992
Mobile ion gettering in passivated P+ polysilicon gates
- C.Y. Wong
- C.C.-H. Hsu
- et al.
- 1990
- VLSI Technology 1990
A high-performance 0.5-μm BiCMOS technology with 3.3-V CMOS devices
- Eric D. Johnson
- T.B. Hook
- et al.
- 1990
- VLSI Technology 1990
Full-swing complementary BiCMOS logic circuits
- Hyun J. Shin
- Chih-Liang Chen
- et al.
- 1989
- Bipolar Circuits and Technology Meeting 1989
Study of boron penetration through thin oxide with p+-polysilicon gate
- J.Y.-C. Sun
- C.Y. Wong
- et al.
- 1989
- VLSI Technology 1989