A 0.063 μm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch
- Veeraraghvan S. Basker
- Theodorus E. Standaert
- et al.
- 2010
- VLSI Technology 2010
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29 results for Pranita Kulkarni
Stress liner proximity technique to enhance carrier mobility in high-κ metal gate MOSFETs
- Dechao Guo
- Kathryn Schonenberg
- et al.
- 2009
- MRS Fall Meeting 2009
Sub-20 nm abrupt USJ formation with long ms-flash with sub-2 nm dopant motion control
- Kam-Leung Lee
- Isaac Lauer
- et al.
- 2010
- IWJT 2010
Extraction of effective oxide thickness for SOI FINFETs with high-κ/Metal gates using the body effect
- Sujata Paul
- Frank Yeh
- et al.
- 2010
- IEEE Electron Device Letters
Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond
- Ali Khakifirooz
- Kangguo Cheng
- et al.
- 2010
- ISSCC 2010
Challenges and solutions of extremely thin SOI (ETSOI) for CMOS scaling to 22nm node and beyond
- Kangguo Cheng
- Ali Khakifirooz
- et al.
- 2010
- CSTIC 2010
Strain engineering for fully-depleted SOI devices
- Ali Khakifirooz
- Pranita Kulkarni
- et al.
- 2010
- ECS Transactions
Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications
- K. Cheng
- A. Khakifirooz
- et al.
- 2009
- IEDM 2009
Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drain
- K. Cheng
- A. Khakifirooz
- et al.
- 2009
- VLSI Technology 2009