High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography
- S. Narasimha
- K. Onishi
- et al.
- 2006
- IEDM 2006
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8 results for M. Weybright
High performance and low power transistors integrated in 65nm bulk CMOS technology
- Z. Luo
- A. Steegen
- et al.
- 2004
- IEDM 2004
10nm FINFET technology for low power and high performance applications
- D. Guo
- H. Shang
- et al.
- 2014
- ICSICT 2014
High performance bulk planar 20nm CMOS technology for low power mobile applications
- Huiling Shang
- Sameer Jain
- et al.
- 2012
- VLSI Technology 2012
SRAM Cell Design for Stability Methodology
- Clement Wann
- Robert Wong
- et al.
- 2005
- VLSI Technology 2005
Super-halo asymmetric vertical pass transistor design for ultra-dense DRAM technologies
- D. Chidambarrao
- K. McStay
- et al.
- 2003
- VLSI-TSA 2003
Evaluation of X-ray lithography using a 0.175 μm (0.245 μm2 cell area) 1 Gb DRAM technology
- Rosemary Longo
- S. Chaloux
- et al.
- 1998
- VLSI Technology 1998
0.21 μm2 7F2 trench cell with a locally-open globally-folded dual bitline for 1 Gb/4 Gb DRAM
- C. Radens
- U. Gruening
- et al.
- 1998
- VLSI Technology 1998