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Novel approach to reduce source/drain series and contact resistance in high-performance UTSOI CMOS devices using selective electrodeless CoWP or CoB processJames PanAnna Topolet al.2007IEEE Electron Device Letters
Novel approach to reduce source/drain series resistance in high performance CMOS devices using self-aligned CoWP process for 45nm node UTSOI transistors with 20nm gate lengthJames PanAnna Topolet al.2006VLSI Technology 2006
CVD rhenium and PVD tantalum gate MOSFETs fabricated with a replacement techniqueJames PanDon Canaperiet al.2004IEEE Electron Device Letters