Novel approach to reduce source/drain series and contact resistance in high-performance UTSOI CMOS devices using selective electrodeless CoWP or CoB process
- James Pan
- Anna Topol
- et al.
- 2007
- IEEE Electron Device Letters
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4 results for Ming-Ren Lin
CVD rhenium and PVD tantalum gate MOSFETs fabricated with a replacement technique
- James Pan
- Don Canaperi
- et al.
- 2004
- IEEE Electron Device Letters
Correlation of Id- and Ig-random telegraph noise to positive bias temperature instability in scaled high-κ/metal gate n-type MOSFETs
- Chia-Yu Chen
- Qiushi Ran
- et al.
- 2011
- IRPS 2011
Novel approach to reduce source/drain series resistance in high performance CMOS devices using self-aligned CoWP process for 45nm node UTSOI transistors with 20nm gate length
- James Pan
- Anna Topol
- et al.
- 2006
- VLSI Technology 2006