A gradient descent bias optimizer for oscillator phase noise reduction demonstrated in 45nm and 32nm SOI CMOS
- Mark Ferriss
- Bodhisatwa Sadhu
- et al.
- 2018
- RFIC 2018
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23 results for Daniel Friedman
A 28-GHz 32-Element TRX Phased-Array IC with Concurrent Dual-Polarized Operation and Orthogonal Phase and Gain Control for 5G Communications
- Bodhisatwa Sadhu
- Yahya Tousi
- et al.
- 2017
- IEEE JSSC
Very low voltage (VLV) design
- Ramon Bertran
- Pradip Bose
- et al.
- 2017
- ICCD 2017
A 28GHz 32-element phased-array transceiver IC with concurrent dual polarized beams and 1.4 degree beam-steering resolution for 5G communication
- Bodhisatwa Sadhu
- Yahya Tousi
- et al.
- 2017
- ISSCC 2017
A 1.8 pJ/bit 16 × 16Gb/s source-synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration
- Timothy O. Dickson
- Yong Liu
- et al.
- 2016
- IEEE JSSC
A 60GHz packaged switched beam 32nm CMOS TRX with broad spatial coverage, 17.1dBm peak EIRP, 6.1dB NF at < 250mW
- Bodhisatwa Sadhu
- Alberto Valdes-Garcia
- et al.
- 2016
- RFIC 2016
A 12-to-26GHz fractional-N PLL with dual continuous tuning LC-D/VCOs
- Mark Ferriss
- Bodhisatwa Sadhu
- et al.
- 2016
- ISSCC 2016
A 1.8-pJ/bit 16x16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration
- Timothy O. Dickson
- Yong Liu
- et al.
- 2015
- CICC 2015
A 18mW, 3.3dB NF, 60GHz LNA in 32nm SOI CMOS technology with autonomic NF calibration
- Jean-Olivier Plouchart
- Fa Wang
- et al.
- 2015
- RFIC 2015
A capacitance boosted full-octave LC VCO based 0.7 to 24 GHz fractional-N synthesizer
- Bodhisatwa Sadhu
- Mark Ferriss
- et al.
- 2015
- RFIC 2015