A 22 Gbit/s PAM-4 receiver in 90nm CMOS-SOI technology
- Thomas Toifl
- Christian Menolfi
- et al.
- 2005
- VLSI Circuits 2005
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3 results at VLSI Circuits 2005
4.0GHz 0.18.μm CMOS PLL based on an interpolative oscillator
- Fadi H. Gebara
- Jeremy D. Schaub
- et al.
- 2005
- VLSI Circuits 2005
The circuits and physical design of the synergistic processor element of a CELL processor
- O. Takahashi
- R. Cook
- et al.
- 2005
- VLSI Circuits 2005