The circuit design of the synergistic processor element of a CELL processorO. TakahashiR. Cooket al.2005ICCAD 2005
Discrete Vt assignment and gate sizing using a self-snapping continuous formulationSaumil ShahAshish Srivastavaet al.2005ICCAD 2005
Gate sizing using incremental parameterized statistical timing analysisM.R. GuthausN. Venkateswarantet al.2005ICCAD 2005