TESTABILITY DESIGN FOR MICRO/370, A SYSTEM/370 SINGLE-CHIP MICROPROCESSOR.F.Warren ShihH.H. Chaoet al.1985IEEE ITC 1985
EFFICIENT FAULT SIMULATION OF CMOS CIRCUITS WITH ACCURATE MODELS.Z. BarzilaiJ.Lawrence Carteret al.1985IEEE ITC 1985
TRIM: TESTABILITY RANGE BY IGNORING THE MEMORY.Larry CarterLeendert M. Huismanet al.1985IEEE ITC 1985