Signal and power integrity (SPI) co-analysis for high-speed communication channels
- Renato Rimolo-Donadio
- Xiaomin Duan
- et al.
- 2013
- DesignCon 2013
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4 results at DesignCon 2013
Power supply noise induced jitter estimation in high speed clock tree for full chip timing analysis
- Wen Yin
- Zegui Pang
- et al.
- 2013
- DesignCon 2013
Terabit/s packaging design for testing of high-speed IC transceivers
- Christian Baks
- Renato Rimolo-Donadio
- et al.
- 2013
- DesignCon 2013
Design and experimental validation of compact common mode filter based on EBG technology
- Xiaoxiong Gu
- Renato Rimolo-Donadio
- et al.
- 2013
- DesignCon 2013