Victor Chan

Title

Yield learning & Diag Eng Prof

Victor Chan

Bio

Current / Recent: STSM in Yield / characterization of 2nm Nanosheet Logic; Analog AI hardware and chiplet technologies.
Working in semiconductor industry over 20 years in IBM.
Technical leadership in FEOL integration and device teams of CMOS 90 to deep sub-micron in bulk / SOI technologies, innovative and inventive delivery of process technologies from concept to qualification to manufacturing.
Specialties include semiconductor device & integration in R&D and production, product - customer deployment, technology licensing and technical support. Extensive experience in running lots and characterization of device / inline-metrology / PLY / Health-of-line and yield data. Device, SRAM and product yield learning and improvement through Hands-on data analysis.

Publications

Interaction of middle-of-line (MOL) temperature and mechanical stress on 90nm hi-speed device performance and reliability
- - K.Y. Lim
  - V. Chan
  - et al.
- 2005
- ESSDERC 2005
Dual stress liner enhancement in hybrid orientation technology
- - C. Sheraw
  - M. Yang
  - et al.
- 2005
- VLSI Technology 2005
On the scalability and carrier transport of advanced CMOS devices
- - Meikei Ieong
  - Leland Chang
  - et al.
- 2005
- ICICDT 2005
Strain for CMOS performance improvement
- - Victor Chan
  - Ken Rim
  - et al.
- 2005
- CICC 2005
High performance and low power transistors integrated in 65nm bulk CMOS technology
- - Z. Luo
  - A. Steegen
  - et al.
- 2004
- IEDM 2004
On the integration of CMOS with hybrid crystal orientations
- - M. Yang
  - V. Chan
  - et al.
- 2004
- VLSI Technology 2004
High Performance CMOS Fabricated on Hybrid Substrate with Different Crystal Orientations
- - M. Yang
  - M. Ieong
  - et al.
- 2003
- IEDM 2003
Three dimensional CMOS devices and integrated circuits
- - Meikei Ieong
  - Kathryn W. Guarini
  - et al.
- 2003
- CICC 2003

Visit Google Scholar

Patents

- 04 Dec 2017
- US
- 9837351
Avoiding Gate Metal Via Shorting To Source Or Drain Contacts
- 28 Aug 2017
- US
- 9748358
Gap Fill Of Metal Stack In Replacement Gate Process
- 03 Mar 2015
- US
- 8969969
High Threshold Voltage Nmos Transistors For Low Power Ic Technology
- 06 Jan 2015
- US
- 8927361
High Threshold Voltage Nmos Transistors For Low Power Ic Technology
- 09 May 2014
- JP
- 5536340
Semiconductor Transistors With Expanded Top Portions Of Gates
- 11 Mar 2014
- TW
- I430329
Enhancement Of Electron And Hole Mobilities In <110> Si Under Biaxial Compressive Strain
- 13 Nov 2013
- CN
- ZL200780001792.2
Semiconductor Transistors With Expanded Top Portions Of Gates
- 01 Aug 2013
- TW
- I404210
Semiconductor Transistors With Expanded Top Portions Of Gates
- 18 Jun 2013
- US
- 8466503
Semiconductor Transistors With Expanded Top Portions Of Gates
- 01 Feb 2013
- JP
- 5190201
Enhancement Of Electron And Hole Mobilities In <110> Si Under Biaxial Compressive Strain

Top collaborators

VN

Vijay Narayanan

Vijay Narayanan

IBM Fellow & Strategist, Physics of AI. Senior Manager, PCM and AI Materials

GB

Geoffrey Burr

Geoffrey Burr

Distinguished RSM

IA

Ishtiaq Ahsan

Ishtiaq Ahsan

Senior Manager, Yield/ Test & Characterization, IBM Semiconductor Technology Research & Development