Rajiv Joshi, Rouwaida Kanj, et al.
ESSDERC 2006
An NTL circuit with a charge-buffered active-pulldown emitter-follower stage is described. The circuit utilizes the diffusion capacitance of a charge-storage diode (CSD) as the coupling element between the common-emitter node of the switching transistors and the base of an active-pull-down n-p-n transistor to generate a large dynamic current for the pull-down transistor and to provide a speedup effect on the switching logic stage. Implemented in a 0.8-μm double-poly trench-isolated selfaligned bipolar process, unloaded gate delays of 12.8 ps/1.0 mW, 15.4 ps/0.71 mW, and 18.0 ps/0.53 mW have been achieved. © 1992 IEEE
Rajiv Joshi, Rouwaida Kanj, et al.
ESSDERC 2006
G.P. Li, E. Hackbarth, et al.
IEEE T-ED
G.P. Li, Tze-Chiang Chen, et al.
IEEE Electron Device Letters
Meng-Hsueh Chiang, Keunwoo Kim, et al.
IEEE Transactions on Electron Devices