A 1.2 ns/1 ns 1 K∗16 ECL dual-port cache RAM
- Hyun J. Shin
- P.F. Lu
- et al.
- 1993
- ISSCC 1993
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19 results for Ken Chin
A 5Gb/s 16×16 Si-bipolar crosspoint switch
- Hyun Shin
- James Warnock
- et al.
- 1992
- ISSCC 1992
23 ps/2.1 mW ECL gate
- Kai-Yap Toh
- C.T. Chuang
- et al.
- 1989
- ISSCC 1989
Sub-300-ps CBL Circuits
- S.K. Wiedmann
- Tze Chiang Chen
- et al.
- 1989
- IEEE Electron Device Letters
Ncon-quasi-static effects in advanced high-speed bipolar circuits
- B.S. Wu
- C.T. Chuang
- et al.
- 1992
- CICC 1992
Sub-15 ps charge-buffered active-pull-down ECL/NTL circuits
- Ken Chin
- Ching-Te Chuang
- et al.
- 1992
- CICC 1992
High-speed low-power ECL circuit with AC-coupled self-biased dynamic current source and active-pull-down emitter-follower stage
- C.T. Chuang
- Ken Chin
- et al.
- 1992
- CICC 1992
Power partition and emitter size optimization for bipolar ECL circuit
- H.Y. Hsieh
- Ken Chin
- et al.
- 1992
- BCTM 1992
High-speed low-power charge-buffered active-pull-down ECL circuit
- C.T. Chuang
- Ken Chin
- 1990
- Bipolar Circuits and Technology Meeting 1990
A 1.9 ns/6.3 W/256 Kb bipolar SRAM design
- Kai-Yap Toh
- C.T. Chuang
- et al.
- 1990
- Bipolar Circuits and Technology Meeting 1990