R.V. Joshi, K. Kroell, et al.
VLSID/Embedded 2004
An ECL circuit with a charge-buffered active-pull-down emitter-follower stage is described. Implemented in a 0-8 /an double-poly trench-isolated selfaligned bipolar process, unloaded gate delays of 14.9ps/2.2mW, 20.7ps/1.2mW, and 24.5ps/0.77mW have been achieved. © 1992, The Institution of Electrical Engineers. All rights reserved.
R.V. Joshi, K. Kroell, et al.
VLSID/Embedded 2004
Ken Chin, Ching-Te Chuang, et al.
CICC 1992
D.D. Awschalom, J. Warnock, et al.
Journal of Applied Physics
Hyun J. Shin, P.F. Lu, et al.
ISSCC 1993