B.S. Wu, C.T. Chuang, et al.
CICC 1992
Paper
14.9 ps/2.2 mW charge-buffered active-pull-down ECL circuit
Abstract
An ECL circuit with a charge-buffered active-pull-down emitter-follower stage is described. Implemented in a 0-8 /an double-poly trench-isolated selfaligned bipolar process, unloaded gate delays of 14.9ps/2.2mW, 20.7ps/1.2mW, and 24.5ps/0.77mW have been achieved. © 1992, The Institution of Electrical Engineers. All rights reserved.
Related
Conference paper
High-speed low-power cross-coupled active-pull-down ECL circuit
C.T. Chuang, B.S. Wu, et al.
BCTM 1993
C.T. Chuang, Ken Chin, et al.
IEEE Journal of Solid-State Circuits
R. Puri, C.T. Chuang
IEEE International SOI Conference 1998