5.75 to 44Gb/s quarter rate CDR with data rate selection in 90nm bulk CMOS

Abstract

This paper presents a quarter rate clock/data recovery (CDR) circuit for plesiochronous serial I/O-links. This 2x-oversampled phase-tracking CDR, implemented in 90nm bulk CMOS technology, covers the whole range of data rates from 5.75 to 44Gb/s thanks to a data rate selection logic. A bit error rate < 10-12 was verified up to 38Gb/s using a 27-1 PRBS pattern. The CDR is able to track a maximum frequency deviation of ±615ppm between incoming data and reference clock. © 2008 IEEE.