A 19gb/s 38mW 1-tap speculative DFE receiver in 90nm CMOS
Didem Z. Turker, Alexander Rylyakov, et al.
VLSI Circuits 2009
A static frequency divider designed in a 210-GHz fT, 0.13-μm SiGe bipolar technology is reported. At a -5.5-V power supply, the circuit consumes 44 mA per latch (140 mA total for the chip, with input-output stages). With single-ended sine wave clock input, the divider is operational from 7.5 to 91.6 GHz. Differential clocking under the same conditions extends the frequency range to 96.6 GHz. At -5.0 V and 100 mA total current (28 mA per latch), the divider operates from 2 to 85.2 GHz (single-ended sine wave input).
Didem Z. Turker, Alexander Rylyakov, et al.
VLSI Circuits 2009
Jose Tierno, Alexander Rylyakov, et al.
VLSI Circuits 2010
Behnam Analui, Alexander Rylyakov, et al.
IEEE Journal of Solid-State Circuits
Brian A. Floyd, Scott K. Reynolds, et al.
IEEE Journal of Solid-State Circuits