S.K. Wiedmann, Tze Chiang Chen, et al.
IEEE Electron Device Letters
A bipolar 512 x 10-bit ECL RAM with an access time of 1.0 ns and a power dissipation of 2.4 W. achieving an access-time power/bit product of 0.48 pJ/bit, has been developed. The RAM was fabricated using an advanced bipolar technology featuring poly-base self-alignment, poly-emitter shallow profile, and silicon-filled trench isolation with a minimum mask dimension of 1.2 µm. A Schottky-clamped multi-emitter cell with a cell size of 760 µm2 is obtained as a result of compact cell layout and the use of 1.2-µm trench isolation. Copyright © 1986 by the Institute of Electrical and Electronics Engineers, Inc.
S.K. Wiedmann, Tze Chiang Chen, et al.
IEEE Electron Device Letters
Meng-Hsueh Chiang, Tze-Neng Lin, et al.
IEEE SOI 2006
Keunwoo Kim, R.V. Joshi, et al.
ISLPED 2003
Meng-Hsueh Chiang, Keunwoo Kim, et al.
IEEE International SOI Conference 2005