A 1.2 ns/1 ns 1 K∗16 ECL dual-port cache RAM

Abstract

An experimental 1-k∗16 ECL (emitter coupled logic) dual-port cache RAM block that has a read/write port and an independently accessible read-only port is presented. Multiples of this block can be used to construct a high-performance, large-capacity cache memory. This dual-port memory cell is constructed by adding a differential emitter-coupled sense circuit for the read-only port to the p-n-p-load (or SCR-Type) bipolar read/write single-port cell. The p-n-p-load cell is chosen because of its smaller area and better soft-error immunity than other types of bipolar memory cells. The cache block is fabricated using a 0.8-mu m, trench-isolated, double-poly, self-Aligned 3.6-V Si-bipolar technology with double metal layers and a W local-interconnection layer.