Alexander Rylyakov, Thomas Zwick
IEEE Journal of Solid-State Circuits
A low-power quarter-rate sampling 2-tap DFE is realized for short I/O links. An analog sampling and soft-decision technique is used instead of look-ahead architectures to relax the critical path, and thus saving the power from the redundant paths. No errors are observed with 231-1 PRBS at 6Gb/s, with 80-mV differential launch amplitude through a channel with 6.2-dB attenuation at 3GHz. The receiver draws 4.8mA from a 1.0-V supply. © 2006 IEEE.
Alexander Rylyakov, Thomas Zwick
IEEE Journal of Solid-State Circuits
Mark Ferriss, Alexander Rylyakov, et al.
VLSI Circuits 2013
Sergey Rylov, Alexander Rylyakov
BCTM 2003
Azita Emami-Neyestanak, Aida Varzaghani, et al.
VLSI Circuits 2006