Rex Berridge, Robert M. Averill III, et al.
IBM J. Res. Dev
A global clock distribution strategy used on several microprocessor chips is described. The clock network consists of buffered tunable trees or treelike networks, with the final level of trees all driving a single common grid covering most of the chip. This topology combines advantages of both trees and grids. A new tuning method was required to efficiently tune such a large strongly connected interconnect network consisting of up to 6 m of wire and modeled with 50 000 resistors, capacitors, and inductors. Variations are described to handle different floor-planning styles. Global clock skew as low as 22 ps on large microprocessor chips has been measured.
Rex Berridge, Robert M. Averill III, et al.
IBM J. Res. Dev
Phillip J. Restle, Albert Ruehli, et al.
ADMETA 2000
Steven C. Chan, Kenneth L. Shepard, et al.
IEEE Journal of Solid-State Circuits
Phillip J. Restle, Albert E. Ruehli, et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems