'Timing Closure by Design,' a high frequency microprocessor design methodology
- S.D. Posluszny
- Naoaki Aoki
- et al.
- 2000
- DAC 2000
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11 results for David Boerstler
A 1V 18GHz clock generator in a 65nm PD-SOI technology
- Fadi H. Gebara
- Jeremy D. Schaub
- et al.
- 2007
- ISSCC 2007
A 1GHz single-issue 64b powerPC processor
- H.P. Hofstee
- Naoaki Aoki
- et al.
- 2000
- ISSCC 2000
The 12-core POWER8™ processor with 7.6 Tb/s IO bandwidth, integrated voltage regulation, and resonant clocking
- Eric J. Fluhr
- Steve Baumgartner
- et al.
- 2015
- IEEE JSSC
On-chip circuit for measuring multi-GHz clock signal waveforms
- Keith A. Jenkins
- P. Restle
- et al.
- 2013
- VTS 2013
Design methodology for a 1.0 GHz microprocessor
- S.D. Posluszny
- Naoaki Aoki
- et al.
- 1998
- ICCD 1998
Phase-locked loop clock generator for a 1 GHz microprocessor
- D. Boerstler
- Keith A. Jenkins
- 1998
- VLSI Circuits 1998
Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor
- D.C. Pham
- T. Aipperspach
- et al.
- 2006
- IEEE Journal of Solid-State Circuits
A clock distribution network for microprocessors
- Phillip J. Restle
- Timothy G. McNamara
- et al.
- 2001
- IEEE Journal of Solid-State Circuits
Low-jitter PLL clock generator for microprocessors with lock range of 340-612 MHz
- David W. Boerstler
- 1999
- IEEE Journal of Solid-State Circuits