A generic micro-architectural test plan approach for microprocessor verification

Abstract

Modern microprocessors share several common types of micro-architectural building blocks. The rising complexity of the micro-architecture increases the risk of bugs and the difficulty of achieving comprehensive verification. We propose a methodology to exploit the commonality in the different microprocessors to create a design-independent micro-architectural test plan. Our method allows the testing of the huge micro-architectural test space by using systematic partitioning, which offers a high level of comprehensiveness of the tested behaviors. We show how this method was used to find bugs during verification of an actual high-end microprocessor. Our results show the advantages of this approach over the more traditional test methods that use design specific test plans or that use tools with little micro-architectural knowledge for covering micro-architectural aspects of the design. Copyright 2005 ACM.