A GHz-digital clock jitters in time and frequency

Abstract

The GHz-digital clock jitter measurement capabilities in time and frequency domains are explored. A 101-stage inverter-based ring oscillator implemented in 65nm SOI is used as a clock source. Both domains produce clock period jitters reliably. Cycle-to-cycle jitters are obtained in time, and confirmed in frequency domain. Time interval error jitters are calculated from phase noise, and time-domain results are matched with frequency-dependent jitters. The convergence and limitations of time and frequency-domain jitter measurements are presented. ©2007 IEEE.