Conference paper
A 75GHz PLL front-end integration in 65nm SOI CMOS technology
Daeik Kim, Jonghae Kim, et al.
VLSI Circuits 2007
A 90-nm silicon-on-insulator (SOI) CMOS system on-chip integrates high-performance FETs with 243-GHz Ft, 208-GHz Fmax, 1.45-mS/μm gm, and sub 1.1-dB NFmin up to 26 GHz. Inductor Q of 20, VNCAP of 1.8-fF/μm2, varactor with a tuning range as high as 25:1, and a low-loss microstrip. Transmission lines were successfully integrated without extra masks and processing steps. SOI and its low parasitic junction capacitance enables this high level of performance and will expand the use of CMOS for millimeter-wave applications. © 2005 IEEE.
Daeik Kim, Jonghae Kim, et al.
VLSI Circuits 2007
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IBM J. Res. Dev
Jeong-Il Kim, Daeik Kim, et al.
CICC 2007
David I. Sanderson, Jonghae Kim, et al.
ICSICT 2006