A high-performance, low leakage, and stable SRAM row-based back-gate biasing scheme in FinFET technology

Abstract

This paper describes back-gate biasing scheme using independent-gate controlled asymmetrical (n+/p+ polysilicon gates) FinFET cross s sign devices and its applications to 6-T and 8-T SRAM. Row-based above-VDD/below-GND bias is applied to the back-gates of the access and pull-down cell nFETs to enhance the Read/Write performance, reduce standby leakage, and mitigate process (VT) variability. The application of the technique to stacked Read transistors in 8-T SRAM is also discussed. © 2007 IEEE.