Parasitic Resistance Reduction Strategies for Advanced CMOS FinFETs beyond 7nm
- Heng Wu
- Oleg Gluschenkov
- et al.
- 2018
- IEDM 2018
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48 results for E. Nowak
Accurate performance evaluation for the horizontal nanosheet standard-cell design space beyond 7nm technology
- Yoo-Mi Lee
- Myung-Hee Na
- et al.
- 2017
- IEDM 2017
Off-state self-heating, micro-hot-spots, and stress-induced device considerations in scaled technologies
- Siyu Koswatta
- N. Mavilla
- et al.
- 2015
- IEDM 2015
Bottom oxidation through STI (BOTS) - A novel approach to fabricate dielectric isolated FinFETs on bulk substrates
- K. Cheng
- S.-C. Seo
- et al.
- 2014
- VLSI Technology 2014
SOI FinFET versus bulk FinFET for 10nm and below
- Terence B. Hook
- F. Allibert
- et al.
- 2014
- S3S 2014
Modeling and characterization of gate leakage in high-K metal gate technology-Based embedded DRAM
- Mohit Bajaj
- Rajan K. Pandey
- et al.
- 2013
- IEEE T-ED
Experimental analysis and modeling of self heating effect in dielectric isolated planar and fin devices
- S. Lee
- Richard A. Wachnik
- et al.
- 2013
- VLSI Technology 2013
Revisiting the impact on sub-threshold regions in uniaxially-strained FETs
- M.H. Na
- K. Mcstay
- et al.
- 2013
- CSTIC 2013
Chip-level power-performance optimization through thermally-driven across-chip variation (ACV) reduction
- X. Yu
- Oleg Gluschenkov
- et al.
- 2011
- IEDM 2011
Crystallographic-orientation-dependent gate-induced drain leakage in nanoscale MOSFETs
- Rajan K. Pandey
- Kota V. R. M. Murali
- et al.
- 2010
- IEEE T-ED