A wide power-supply range (0.5V-to-1.3V) wide tuning range (500 MHz-to-8 GHz) all-static CMOS AD PLL in 65nm SOI

An all-static CMOS 65nm SOI ADPLL has a fully programmable loop filter and a 3rd-order ΔΣ modulator. The DCO is a 3-stage, static-inverter-based ring-oscillator programmable in 768 frequency steps. The ADPLL locks from 500MHz to 8GHz at 1.3V 25°C, and 90MHz to 1.2GHz at 0.5V 100°C. The area is 200×150μm2 and it dissipates 8mW/GHz at 1.2V and 1.6mW/GHz at 0.5V. The synthesized 4GHz clock has period jitter of 0.7psrms, and long-term jitter of 6psrms. The phase noise is -110dBc/Hz at 10MHz offset. © 2007 IEEE.