A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI
- Yong Liu
- Ping-Hsuan Hsieh
- et al.
- 2013
- ISSCC 2013
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45 results for Jose A. Tierno
A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS
- Ankur Agrawal
- John Bulzacchelli
- et al.
- 2012
- ISSCC 2012
Bang-bang digital PLLS at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications
- A. Rylyakov
- J. Tierno
- et al.
- 2009
- ISSCC 2009
A modular all-digital PLL architecture enabling both 1-to-2GHz and 24-to-32GHz operation in 65NM CMOS
- A. Rylyakov
- J. Tierno
- et al.
- 2008
- ISSCC 2008
A wide power-supply range (0.5V-to-1.3V) wide tuning range (500 MHz-to-8 GHz) all-static CMOS AD PLL in 65nm SOI
- A. Rylyakov
- J. Tierno
- et al.
- 2007
- ISSCC 2007
Differential 4-tap and 7-tap transverse filters in SiGe for 10Gb/s multimode fiber optic link equalization
- H. Wu
- J. Tierno
- et al.
- 2003
- ISSCC 2003
A 1.3 GSample/s 10-tap full-rate variable latency self-timed FIR filter with clocked interfaces
- Jose Tierno
- Alexander Rylyakov
- et al.
- 2002
- ISSCC 2002
A 1.3 Gsample/s 10-tap full-rate variable-latency self-timed FIR filter with clocked interfaces
- Jose Tierno
- Alexander Rylyakov
- et al.
- 2002
- ISSCC 2002
A 2.3GSample/s 10-tap digital FIR filter for magnetic recording read channels
- S. Rylov
- A. Rylyakov
- et al.
- 2001
- ISSCC 2001
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology
- Timothy O. Dickson
- Yong Liu
- et al.
- 2015
- IEEE JSSC