Advanced Cu/low-k BEOL integration, reliability, and extendibility

Abstract

This talk will be a detailed discussion of technical aspects of Cu BEOL wiring that may be helpful or essential to preserve it successful migration path. The focus will be on BEOL architecture, integration techniques, their impact on reliability, and their outlooks for 32 nm. The talk will mainly call on new data produced by our Research and Development organizations and their associated alliances. Since its first product introduction in late 1997, Cu wiring for CMOS chips has become the industry standard for Logic, ASICs, Foundry, and even a portion of the Memory chip markets. At the most general level, the basic definition of a Cu damascene interconnect has not changed since first published in 1986 by Hu et al. Damascene structure, Ta-based liners, PECVD dielectrics, nitrided insulator caps, W contacts, and various degrees of hierarchical scaling. Detailed differences do exist for various solutions. For example, single vs. dual damascene, the details of the dual damascene patterning schemes, recessed vs. flat vias, CMP hardmask or not, trench etchstop or not, hybrid or uniform dielectric, and removal or not of low-k surface damage. IBM has maintained dual damascene, direct CMP, and no trench etch stop since inception of dual damascene for W in 1984. For Cu, we have also retained the bilayer TaN/Ta liner and SiN or SiCN caps. We switched from trench-first to via-first in 130 nm, and added a novel LTO (low-temperature oxide) barrier film to the sacrificial RIE stack for low-k via-first in 90 nm - this LTO scheme is now entering its 4th generation in 32 nm. The LTO layer completely shuts down resist poisoning, extends resist etch budget, allows for conventional rework, and patterning by conventional dielectric RIE chemistries and tooling. For the best Cu reliability, we remove low-k surface damage, which obviously requires slight pre-compensation by negative process bias (litho and/or RIE) for slight CD increase. For all this history, the BEOL insulator has been based on PECVD silicate glasses with various dopings, densities, and dielectric constants. Our qualified films have extended from k=4.1 to 3.6, 3.0, 2.7, and 2.4, and are currently being demonstrated at 2.2 and 2.0. AU low-k films are significantly improved in electrical, mechanical, and chemical properties relative to corresponding commercial films. Fundamental reliability innovations have come in time to preserve this roadmap, to solve weaknesses in E-M, S-M, CPI, and TDDB. These include via recessing, low-k damage removal, low-k adhesion, crackstop engineering, and theoretical mechanical developments. New data on these will be discussed in detail, with some being presented in companion papers in this conference. For 32 nm, two fundamental scaling issues become limiting for the first time, namely, Cu E-M requiring a stronger Cu/cap interface, and W contact resistances, calling for significant W improvements or a new contact metallization. Experimental solutions have been demonstrated, and data will be discussed here. But these need to be proven at higher levels to be considered production-worthy. ©2007 IEEE.