Donald Samuels, Ian Stobert
SPIE Photomask Technology + EUV Lithography 2007
Resolution enhancement techniques and higher NA exposure are employed to meet the lithographic requirements imposed by aggressive shrinks to chip feature sizes. For certain critical levels, like storage and isolation patterning of DRAM devices, the capability to exactly reproduce the mask layout is limited. Severe corner rounding and line image shortening can occur. Such phenomena can be significant contributors to side effects like current leakage, inadequate retention time, stress, and perhaps yield loss. Our development work has shown that the use of Serif and Hammerhead structures can improve resolution printing. Moreover, better process latitude and CD control can be achieved. This paper gives an overview of these innovative techniques. It includes the consideration of different design layouts based on simulations, as well as mask making limitations e.g. mask inspection capability. The benefits of these techniques are discussed and illustrated with detailed lithographic performance data and SEM pictures. © 2000 SPIE-The International Society for Optical Engineering.
Donald Samuels, Ian Stobert
SPIE Photomask Technology + EUV Lithography 2007
Salvatore Certo, Anh Pham, et al.
Quantum Machine Intelligence
Robert Manson Sawko, Malgorzata Zimon
SIAM/ASA JUQ
Timothy J. Wiltshire, Joseph P. Kirk, et al.
SPIE Advanced Lithography 1998